

module tb_top;
    // clock / reset
    logic clk;
    logic rst_n;

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end
    initial begin
        rst_n = 0;
        #20 rst_n = 1;
    end

    // instantiate interface instances
    aru_unary_cfg_if u_aru_cfg_if_inst1 ();  // 注意这里实例名可任意
    aru_unary_cfg_if u_aru_cfg_if_inst2 ();
    aru_unary_cfg_if u_aru_cfg_if_inst3 ();
    aru_unary_cfg_if u_aru_cfg_if_inst4 ();
    aru_unary_cfg_if u_aru_cfg_if_inst5 ();
    aru_unary_cfg_if u_aru_cfg_if_inst6 ();


    aru_payload_if u_aru_pld_left_if_inst1 ();
    aru_payload_if u_aru_pld_left_if_inst2 ();
    aru_payload_if u_aru_pld_left_if_inst3 ();
    aru_payload_if u_aru_pld_left_if_inst4 ();
    aru_payload_if u_aru_pld_left_if_inst5 ();
    aru_payload_if u_aru_pld_left_if_inst6 ();


    aru_payload_if u_aru_pld_right_if_inst1 ();
    aru_payload_if u_aru_pld_right_if_inst2 ();
    aru_payload_if u_aru_pld_right_if_inst3 ();
    aru_payload_if u_aru_pld_right_if_inst4 ();
    aru_payload_if u_aru_pld_right_if_inst5 ();
    aru_payload_if u_aru_pld_right_if_inst6 ();


    // DUT 实例化：把 interface instance 传进去（匹配 modport 类型）
    aru_unary_sqrt dut1 (
        .clk               (clk),
        .rst_n             (rst_n),
        .u_aru_cfg_if      (u_aru_cfg_if_inst1),       // 连接接口实例
        .u_aru_pld_left_if (u_aru_pld_left_if_inst1),
        .u_aru_pld_right_if(u_aru_pld_right_if_inst1)
    );

    aru_unary_recp dut2 (
        .clk               (clk),
        .rst_n             (rst_n),
        .u_aru_cfg_if      (u_aru_cfg_if_inst2),       // 连接接口实例
        .u_aru_pld_left_if (u_aru_pld_left_if_inst2),
        .u_aru_pld_right_if(u_aru_pld_right_if_inst2)
    );

    aru_unary_pow dut3 (
        .clk               (clk),
        .rst_n             (rst_n),
        .u_aru_cfg_if      (u_aru_cfg_if_inst3),       // 连接接口实例
        .u_aru_pld_left_if (u_aru_pld_left_if_inst3),
        .u_aru_pld_right_if(u_aru_pld_right_if_inst3)
    );

    aru_unary_exp dut4 (
        .clk               (clk),
        .rst_n             (rst_n),
        .u_aru_cfg_if      (u_aru_cfg_if_inst4),       // 连接接口实例
        .u_aru_pld_left_if (u_aru_pld_left_if_inst4),
        .u_aru_pld_right_if(u_aru_pld_right_if_inst4)
    );

    aru_unary_clamp dut5 (
        .clk               (clk),
        .rst_n             (rst_n),
        .u_aru_cfg_if      (u_aru_cfg_if_inst5),       // 连接接口实例
        .u_aru_pld_left_if (u_aru_pld_left_if_inst5),
        .u_aru_pld_right_if(u_aru_pld_right_if_inst5)
    );

    aru_unary_neg dut6 (
        .clk               (clk),
        .rst_n             (rst_n),
        .u_aru_cfg_if      (u_aru_cfg_if_inst6),       // 连接接口实例
        .u_aru_pld_left_if (u_aru_pld_left_if_inst6),
        .u_aru_pld_right_if(u_aru_pld_right_if_inst6)
    );


    // （可选）在 tb 里驱动接口信号，或在接口内写 driver/monitor task/class
    initial begin
        #1000 $finish;
    end
endmodule
